The present invention relates to a time measuring system and a time measuring method.
Referring to FIGS. 9 and 10, description will be made at first as regards a conventional time measuring system of this type. The conventional time measuring system comprises a high-speed counter section 1 for counting up a counter value in response to a clock signal between supplies of a measurement start signal and a measurement stop signal to produce a counter output signal representative of the counter value, an adding section 2 connected to the high-speed counter section for executing an adding operation as regards the counter value by the use of the clock signal and the counter output signal to produce a sum total of the counter value, and a data producing section 3 connected to the adding section and the high-speed counter section for producing a resolution datum in response to the sum total by the use of the counter output signal.
The high-frequency pulse generator 1 has a structure as shown in FIG. 11 for achieving pulse processing faster (shorter) than the processing limit speed of a semiconductor product. However, there is a drawback that a counter value deviates by at least .+-.1. The reason for this is that when racing of inputs occurs at an input timing of a flip-flop, an output becomes unstable and it is unknown whether a level of the output is stabilized to high or low after a lapse of a time.
For solving this drawback, an averaging process is carried out using the sum total in which deviations of the counter values are corrected.
Specifically, relative to n signals obtained through different stages of delay buffers 105 in the high-frequency pulse generator 9, m-bit counters 10 (m.gtoreq.4) are provided in n stages (pipeline processing) for deriving an integral part of a mean counter value (.SIGMA./n), and one-bit counters 11 are provided in n stages (pipeline processing) for deriving a decimal part of the mean counter value. Since each of the one-bit counters 11 lacks information about rise to unit from a first bit to a second bit, a first correction circuit 108 is provided as shown in FIG. 12 for carrying out .+-.1 correction to one-bit counter values of 1 and 0 of the one-bit counters 11 and outputting information about rise to unit when the one-bit counter values of the one-bit counters 11 change from 1 to 0.
However, using the one-bit counters for obtaining the decimal parts causes an error in the time measurement accuracy. The reason for occurrence of the error is that since the pipelined one-bit counters are individual circuits, respectively, assuming that the resolution number for the system clock is n, it is possible that each of the n one-bit counters takes three kinds of counter values, that is, Q, Q+1 or Q+2. The counter value of the one-bit counter can only be 0 or 1. For eliminating the error in the time measurement accuracy, a second correction circuit 109 is provided as shown in FIG. 12.
The second correction circuit 109 comprises a selector 110 for selecting a plurality of necessary counter values from among the n pipelined one-bit counter values of the one-bit counters 11, a D-FF 111 for latching a signal from the selector 110, a coincidence circuit 112 for comparing an output from the D-FF 111 and a value obtained by incrementing an output of the D-FF 111 through the coincidence circuit 112 and a D-FF 113, the D-FF 113 for latching an output of the coincidence circuit 112, a zero-detection circuit 114 for carrying out zero detection based on an output value of the D-FF 113 and an output value from a selector section 14 of an adding section 2 via the first correction circuit 108, and a selector 115 for selecting an output of the zero-detection circuit 114 and a counter value of a lower second bit of the m-bit counter 10 from the selector section 14 of the adding section 2, using a control signal for switching an operation process of the adding section 2 between the m-bit side and the one-bit side. By inputting an output of the selector 115 into the adding section 2, an operation of the counter value of Q+2 is made possible.
Subsequently, selection is carried out to derive the sum total of the counter values of the m-bit counters 10 and the sum total of the counter values of the one-bit counters 11. A comparator 118 compares the resolution number n derived at the MPU 102 and the number of addition times derived at an x-bit counter 117 of an operation times control circuit 116 as shown in FIG. 13. A comparison result from the comparator 118 is latched by a D-FF 119 so as to control the number of addition times of the one-bit counters 11.
The number of addition times of the counter values of the m-bit counters 10 is set in advance to be the number of the m-bit counters 10 to be used. The selector section 14 selects an addition times control signal for the m-bit counters 10 or the one-bit counters 11 so as to control the number of addition times.
The counter values of the m-bit counters 10 or the one-bit counters 11 from the selector section 14 are added through a D-FF 15, an ADD 16 a D-FF 17 and a D-FF 18 so as to derive the sum total of the counter values of the m-bit counters 10 or the one-bit counters 11. The derived sum total is stored in a register 19. The data stored in the register 19 are read and written in the MPU 20 at read/write timings of the MPU 20.
At the MPU 20, the sum total of the counter values of the m-bit counters 10 is divided by the number of m-bit counters 10 to be used. On the other hand, with respect to the counter values of the one-bit counters 11, the MPU 20 derives a resolution number n over a period of the clock f based on the number n of one-bit counters 12 (LSB's of the m-bit counters 10 are used, and the one-bit counters 11 are used), and the number of continued counter values of low or high among counter values of the register 19 for controlling the read/write timings of the MPU 20 and the n one-bit counters 12, and controls the number of addition times at the adding section 2 up to n.
Each of the delay buffers 105 used in the high-frequency pulse generator 9 of FIG. 11 is subjected to dispersion in delay time depending on the conditions of source voltage and temperature, and thus the resolution number n varies accordingly. In view of this, the MPU 20 divides the sum total of the counter values of the m-bit counters 10 and the sum total of the counter values of the one-bit counters 11 by the resolution number n so as to derive the mean values thereof, respectively.
The dispersion of the counter values of the pipelined m-bit counters 10 and the dispersion of the counter values of the pipelined one-bit counters 11 during one period of the clock .phi. are not greater than +1 or +2, respectively. Accordingly, the counter value of the one-bit counter 11 becomes a counter value of the one-bit counter 11 when the stage number of the delay buffer in the high-frequency pulse generator 9 of FIG. 11 is the smallest, a +1 counter value or a +2 counter value. The counter value including an element below decimal point becomes a counter value of an LSB or a value of a lower second bit subjected to the +2 correction at the second correction circuit 109 in FIG. 12.
The mean value of the thus derived decimal parts is derived, the mean value of the integral parts is added to the mean value of the decimal parts to derive the sum of the mean values, and this sum is multiplied by a period of the clock .phi. to derive a measured time.
As shown in FIGS. 10 and 14, in response to an input of a signal to be measured, the high-frequency pulse generator 9 produces enable signals EN1 to n, which control the start and the stop of the counting of the m-bit counters 10, the one-bit counters 11 and the one-bit counters 12, based on a given start command and given stop commands STOP1 to STOPn. For n-resolving the system clock .phi., the given stop commands STOP1 to STOPn have n delay times.
The enable signals EN1 to n produced by the given stop commands STOP1 to STOPn are divided into two kinds of values, that is, low and high levels, by the high-frequency pulse generator 9 to control the start and the stop of the counting of the m-bit counters 10, the one-bit counters 11 and the one-bit counters 12 so that the m-bit counter 10 takes two kinds of counter values, that is, Q or Q+1, the one-bit counter 93 takes three kinds of counter values, that is, Q, Q+1 or Q+2, and the one-bit counter 12 takes two kinds of counter values, that is, 0 or 1.
At the MPU 20, the sum total of the counter values Q and Q+1 of the m-bit counters 10 and the counter values of Q, Q+1 and Q+2 of the one-bit counters 11 is divided by the resolution number n derived by the number of the continued values of 0 or 1 among the counter values of the one-bit counters 12 so as to derive a mean counter value, and the derived mean counter value is multiplied by a period of the system clock, so that it is possible to carry out the measurement with accuracy of time shorter than the system clock.
As shown in FIGS. 10, 12 and 15, since the one-bit counters 12 up to the resolution number n take three kinds of counter values of Q, Q+1 and Q+2, it is possible, by applying the +2 correction to one-bit counter values in FIG. 15 through the second correction circuit 109 in FIG. 12 and outputting them, to carry out the measurement with accuracy of time shorter than the system clock using the decimal part counters of one-bit structure. FIGS. 16A and 16B are flowcharts showing operations of the time measuring system shown in FIG. 10.
In the foregoing conventional technique, since the delay buffers are used in a plurality of stages for deriving the values of counting shorter than a period of the system clock (hereinafter also referred to as "decimal parts"), the time measurement accuracy is determined by a delay time per stage of the delay buffer. On the other hand, the delay time of the delay buffer is dispersed in a magnitude of several times due to change in environment, such as temperature or voltage. Accordingly, the dispersion of the delay time of the delay buffer is considered upon designing in view of the operation temperature range and the operation voltage range so as to obtain the required time measurement accuracy. However, since the measurement accuracy is not measured in actual use, a control can not be performed for the case where the required time measurement accuracy is not obtained. Therefore, in the time measuring system or in an extended system using the time measuring system, even if the required time measurement accuracy is not obtained, the time measuring system only outputs the measurement result to, in the extended system, peripheral systems.
Thus, it is possible that the measurement result is not within the required measurement accuracy, and further, it can not be discriminated whether the measurement result is within the required measurement accuracy or not.